1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, especially a NAND-structured flash memory, and in particular relates to a configuration of a core portion of the memory and its control circuit.
2. Description of the Related Art
Recently, an EEPROM (NAND-structured flash memory) having NAND-structured cells has often been used as an EEPROM having a larger capacity in digital devices such as digital cameras and mobile telephones.
Various improvements have been attempted in the NAND-structured flash memory with increasing use thereof. For example, in Jpn. Pat. Appln. KOKAI Publication No. 10-199280, driving is performed with a pair of adjacent bit lines in such a manner that when one of them is in a selected state, the other is in a non-selected state, in order to prevent erroneous operations due to noise or word line delay. In this case, the non-selected bit line is used as a dummy bit line, and data is sensed from the pair of bit lines by a differential amplifier. A dummy cell having a larger on-resistance than a memory cell is connected between the bit line and a source line, and in such a configuration, the dummy cell connected to the non-selected bit line is turned on. Further, the memory cell and the dummy cell are designed such that the dummy bit line indicates a midpoint potential in association with a voltage change of the selected bit line when data “0” and “1” are read.
Furthermore, Jpn. Pat. Appln. KOKAI Publication No. 2002-237194 provides a pre-charging method in which, in order to reduce time to pre-charge the bit lines, two pre-charge sections are provided, and one pre-charge section supplies a data line with a current that can be varied in accordance with voltage changes of the data line, while the other pre-charge section supplies the data line with a constant current irrespective of the voltage changes of the data line.
Incidentally, in a write operation of the NAND-structured flash memory, when the memory cell in the center of a NAND string is the selected cell, the memory cells on both sides thereof are also ordinary memory cells, so that a bias state of several cells around the selected cell is symmetrical. Conversely, when the memory cell at the end of the NAND string is the selected cell, the bias state around the selected cell is asymmetrical because one cell serves as a selection gate. As a result, the characteristics of writing into the memory cell are different in the memory cell next to the selection gate and the other memory cells.
In binary operation with little concern about increasing threshold distribution, the difference in characteristics is not a large problem. However, in the case of multi-level operation such as quaternary, octal and hexadecimal levels, the width of threshold distribution needs to be controlled to narrow the width, and it is therefore desired to have a uniform characteristic of memory cell writing.
If the writing characteristics are different in the memory cell at the end of the NAND string such as the memory cell next to the selection gate, and the memory cell in the center of the NAND string, it is necessary to individually control the voltage applied to a control gate of the memory cell, for example, depending on where the selected cell is located, and thus a complicated control circuit is needed to achieve this.
In addition, for example, step-up writing is utilized at present in which the writing voltage is stepped up to further reduce the width of threshold distribution. However, if the writing characteristics are significantly different in the memory cells, more time is spent in the step-up writing to reduce the width of threshold distribution, leading to lower performance.
Moreover, in writing, if the state of the selected cell should remain unchanged (electric charges should not be injected into a floating gate), a channel of the NAND string is previously charged before a word line is charged to a predetermined voltage.
At this moment, the gate potential of the source line side selection gate is VSS, and the selection gate is in a cut-off state. However, if a predetermined voltage is applied to the memory cell adjacent to the selection gate, the coupling capacitance of the selection gate and the control gate of the memory cell adjacent thereto causes the gate potential of the selection gate to float from VSS. This causes a phenomenon in which the selection gate conducts and the electric charges in the channel are discharged. In this way, “erroneous writing” occurs where a charge is injected into the floating gate of the selected cell whose state should not be changed.
On the other hand, in the NAND-structured flash memory, the size of one cell array tends to be increased directly with increasing capacity, and the length of the word line and bit line is only increasing. This is because array division is avoided as much as possible to reduce chip size to the minimum for cost reduction.
Furthermore, parasitic capacitance and resistance increase along with the increase in the length of the word line and bit line, which is a disadvantage to the performance of a chip, and therefore, some measures need to be taken. For example, the increased bit line length poses such problems that the pre-charge time is increased, that time is increased for a cell current to cause a small potential difference in the bit line, and that time is increased for the bit lines to recover their original state.
Moreover, the following problems are posed in a reading operation of the NAND-structured flash memory. In reading, the selected bit line is pre-charged to a predetermined voltage, and the potential of the non-selected bit line will be VSS which is a bit line shield potential. After the selected bit line has been pre-charged, a bit line side selection gate is opened to discharge the electric charges from the cell to the bit line in accordance with a threshold value (signal) written into the cell connected to the selected word line, and its small potential difference is amplified by a sense amplifier. After it is sensed, the bit line recovers its original potential.
On the other hand, the bit lines on both sides of the selected bit line are non-selected bit lines. Noise due to coupling is reduced in such a manner that the non-selected bit lines have a fixed potential (e.g., VSS) and are used as shielding lines. More specifically, the selected bit line and the non-selected bit lines are alternately arranged, and they are allocated in different pages. They are temporarily differentiated by parity, and respectively called an EVEN page and an ODD page.
In order to decrease the bit line pre-charge time, the non-selected bit line which is currently at VSS may be pre-charged to a pre-charge potential at the same time. The pre-charge time is reduced because the wiring capacitance between effective adjacent lines is eliminated and the wiring capacitance necessary to drive all the bit lines is reduced.
In this case, however, in the conventional structure of the NAND string, when the cell linked to the non-selected bit line serving as a shield has a negative threshold value (“1”), opening the selection gate will cause the current to flow from its bit line to the source line to lower the potential, resulting in a problem that it cannot serve as the shielding line.
Therefore, it has been desired to realize a NAND-structured flash memory capable of accomplishing a uniform writing characteristic of the memory cells by equalizing the writing characteristic of the memory cell at the end of the NAND string with that of the memory cell in the center.
Furthermore, there has also been a desire for a NAND-structured flash memory capable of reducing the pre-charge time in a bit line pre-charge operation when reading or verifying the NAND-structured flash memory.